PD Engineer

• Bangalore, Karnataka, India

• 1547890
• Apr 28, 2023
• 0-25 %
• Hardware Engineering
• Individual Contributor
• Full-Time
• Up to 50% work from home

Microsoft’s Cloud Compute Development Organization (CCDO) is seeking passionate, driven and intellectually curious engineers to join our pre-silicon hardware physical design team, covering RTL to GDS methodology, design convergence, and design quality for our projects. We are responsible for delivering cutting-edge, custom IP and SOC designs that can perform complex and high-performance functions in the most efficient manner. This new team will be involved in numerous projects within Microsoft developing custom silicon for a diverse set of systems.

In this high impact role on the team, you will be responsible to:

• Work closely with top level and block level Physical Design Engineers on analysis and fixes on LVS, DRC (Design Rule Check), ERC (Electrical Rule Check), Antenna, etc.
• Drive full chip integration for physical design verification, signoff, and Tape-outs on the leading-edge technology nodes.
• Collaborating with clock, analog, integration team on definition, implementation, and verification of critical chip routing, power delivery, block integration and other aspects.
• Work with 3pIP (third-party IP) and 1pIP teams for efficient and timely SOC-IP handshake.
• Work with CAD team, tool vendors, foundry, and other external partners to develop and validate new tools, flows, run sets, etc.
• Utilize scripting skills to write and customize tool flows to maximize design efficiency and productivity.

Required:

• BS/MS in Electrical or Computer Engineering/Electrical Engineering
• 5+ years of experience in semiconductor chip design/SOC physical design.
• Excellent communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
• Experience in Physical Verification EDA (Electronic Design Automation) tools like Mentor Calibre and Synopsys ICV.
• Strong Debugging skills for DRC, LVS, ERC, Antenna, High Voltage DRC, ESD, etc.

Preferred:

• Multiple SOC Tape-Out experience in the advanced foundry process nodes.
• Understanding of full chip integration, floor planning, IO RDL, and bump planning.
• Experience and knowledge of physical design flow and industry standard Place and Route tool (Fusion Compiler/Innovus, ICC2, etc.)
• Understanding of transistor/device basics.
• Proficient in scripting languages such as Perl, TCL, Python.
• Strong problem-solving and data analysis skills
• Ability to communicate effectively with cross-functional teams.

#MicrosoftIndia #MicrosoftSiliconPD

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.